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ICL7139, ICL7149
August 1997
3 3/4 Digit, Autoranging Multimeter
Description
The Intersil ICL7139 and ICL7149 are high performance, low power, auto-ranging digital multimeter lCs. Unlike other autoranging multimeter ICs, the ICL7139 and ICL7149 always display the result of a conversion on the correct range. There is no "range hunting" noticeable in the display. The unit will autorange between the four different ranges. A manual switch is used to select the 2 high group ranges. DC current ranges are 4mA and 40mA in the low current group, and 400mA and 4A in the high current group. Resistance measurements are made on 4 ranges, which are divided into two groups. The low resistance ranges are 4/40k. The high resistance ranges are 0.4/4M. Resolution on the lowest range is 1.
Features
* 13 Ranges - ICL7139 - 4 DC Voltage 400mV, 4V, 40V, 400V - 1 AC Voltage 400V - 4 DC Current 4mA, 40mA, 400mA, 4A - 4 Resistance 4k, 40k, 400k, 4M * 18 Ranges - ICL7149 - 4 DC Voltage 400mV, 4V, 40V, 400V - 2 AC Voltage with Optional AC Circuit - 4 DC Current 4mA, 40mA, 400mA, 4A - 4 AC Current with Optional AC Circuit - 4 Resistance 4k, 40k, 400k, 4M * Autoranging - First Reading is Always on Correct Range * On-Chip Duplex LCD Display Drive Including Three Decimal Points and 11 Annunciators * No Additional Active Components Required * Low Power Dissipation - Less than 20mW - 1000 Hour Typical Battery Life * Display Hold Input * Continuity Output Drives Piezoelectric Beeper * Low Battery Annunciator with On-Chip Detection * Guaranteed Zero Reading for 0V Input on All Ranges
Ordering Information
PART NUMBER ICL7139CPL ICL7149CPL ICL7149CM44 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 PACKAGE 40 Ld PDIP 40 Ld PDIP 44 Ld MQFP PKG. NO. E40.6 E40.6 Q44.10x10
Pinouts
ICL7139, ICL7149 (PDIP) TOP VIEW
F1/ DP2 POL/AC BP2 BP1 V+ V1 2 3 4 5 40 ADG3 /E3 B2 /C2 39 B3 /C3 38 F2 /DP3 37 G2 /E2 36 A2 /D2 35 B2 /C2 34 F1 /DP2 33 G1 /E1 32 A1 /D1 31 B1 /C1 30 F0 /DP1 29 G0 /E0 28 A0 /D0 27 B0 /C0 26 LO BAT/V 25 M/A 24 /A VREF LO COMMON INT V/ DEINT INT 1 23 k/m 22 OSC IN 21 OSC OUT TRIPLE POINT CINT CAZ HI VA2 /D2 G2 /E2 F2 /DP3 B3 /C3 ADG3 /E3 POL/AC NC BP2 BP1 V+ NC 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 M/A /A k/m OSC IN OSC OUT HOLD HI-DC/LO-AC V//A mA/A BEEPER OUT NC
ICL7149 (MQFP) TOP VIEW
LO BAT/V F0 /DP1
G1 /E1
G0 /E0
A1 /D1
B1 /C1
A0 /D0
B0 /C0
VREF 6 LO HI DEINT 7 8 9
COMMON 10 INT 1 11 INT V/ 12 TRIPLE POINT 13 CAZ 14 CINT 15 BEEPER OUT 16 mA/A 17 V//A 18 HI-DC/LO-AC 19 HOLD 20
24 10 11 23 12 13 14 15 16 17 18 19 20 21 22
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3088.1
3-33
ICL7139, ICL7149 Functional Block Diagram
SWITCHES
CRYSTAL
OSC
CONTROL LOGIC INCLUDING AUTORANGING LOGIC
BEEPER DRIVER PIEZO ELECTRIC BEEPER DISPLAY DRIVER AND LATCHES
COUNTERS DIGITAL COMMON
DISPLAY
POWER SUPPLY SECTION
ANALOG SECTION ANALOG SWITCHES, INTEGRATION AND COMPARATOR
V+ V- COM
EXTERNAL RESISTORS AND CAPACITORS
3-34
ICL7139, ICL7149
Absolute Maximum Ratings
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Reference Input Voltage (VREF to COM) . . . . . . . . . . . . . . . . . . . 3V Analog Input Current (IN + Current or IN + Voltage) . . . . . . . 100A Clock Input Swing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to V+ -3
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Zero Input Reading
V+ = 9V, TA = 25oC, VREF adjusted for -3.700 reading on DC volts, test circuit as shown in Figure 3. Crystal = 120kHz. (See Figure 14) TEST CONDITIONS VIN or IIN or RIN = 0.00 (Notes 1 and 8) (Notes 1 and 8) (Notes 1 and 8) (Notes 1 and 8) (Notes 1 and 8) (Notes 1 and 8) (Notes 1 and 8) At 60Hz (Notes 5, 7, and 8) RUNKNOWN = Infinity VIN = 0, DC V (Note 2, 95% of Time) VIN = 0, AC V (Note 2, 95% of Time) VIN = 0, DC Voltage Range ICOMMON < 10A ICOMMON < 10A, Temp. = 0oC To 70oC ICOMMON < 10A Average DC < 50mV MIN -00.0 -1 2.7 2.8 VIN = V+ to V- (Note 3) -50 V+ - 0.5 V- + 3 VCLOAD = 10nF Range = Low , VREF = 1.00V V+ to VV+ to V- (Note 4) 7 6.5 TYP -
MAX +00.0 +1 1 0.30 0.75 1 0.75 2.4 3.1 10 3.2 +50 V+ V+ - 2.5 V- + 0.5 100 11 7.5
UNITS V, I, Counts % of RDG 1 % of RDG 1 % of RDG 8 % of RDG 9 % of RDG 1 % of RDG 1 % of RDG V LSB LSB mA V ppm/ oC V Hz A V V V s kHz k V V
Linearity (Best Straight Line) (Note 6) Accuracy DC V, 400V Range Only Accuracy DC V, 400V Range Excluded Accuracy , 4K and 400K Range Accuracy , 4K and 4M Range Accuracy DC I, Unadjusted for Full Scale Accuracy DC I, Adjusted for Full Scale Accuracy AC V Open Circuit Voltage for Measurements Noise Noise Supply Current Analog Common (with Respect to V+) Temperature Coefficient of Analog Common Output Impedance of Analog Common Backplane/Segment Drive Voltage Backplane/Segment Display Frequency Switch Input Current Switch Input Levels (High Trip Point) Switch Input Levels (Mid Trip Point) Switch Input Levels (Low Trip Point) Beeper Output Drive (Rise or Fall Time) Beeper Output Frequency Continuity Detect Power Supply Functional Operation Low Battery Detect
0.2 2 VREF 0.1 4 1.5 2.9 -100 1 3.0 75 25 2 1.5 9 7
NOTES: 1. Accuracy is defined as the worst case deviation from ideal input value including: offset, linearity, and rollover error. 2. Noise is defined as the width of the uncertainty window (where the display will flicker) between two adjacent codes. 3. Applies to pins 17-20. 4. Analog Common falls out of regulation when the Low Battery Detect is asserted, however the ICL7139 and ICL7149 will continue to operate correctly with a supply voltage above 7V and below 11V. 5. For 50Hz use a 100kHz crystal. 6. Guaranteed by design, not tested. 7. ICL7139 only. 8. RDG = Reading.
3-35
ICL7139, ICL7149 Timing Waveform
FIRST AUTO ZERO FIRST INTEGRATE FIRST DEINTEGRATE UNDERRANGE AUTO ZERO SECOND AUTO ZERO SECOND INTEGRATE SECOND DEINTEGRATE UNDERRANGE AUTO ZERO THIRD AUTO ZERO THIRD INTEGRATE THIRD DEINTEGRATE UNDERRANGE AUTO ZERO FOURTH AUTO ZERO FOURTH INTEGRATE FOURTH DEINTEGRATE AUTO ZERO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
FIGURE 1. LINE FREQUENCY CYCLES (1 CYCLE = 1000 INTERNAL CLOCK PULSES = 2000 OSCILLATION CYCLES)
Pin Descriptions
I/O O O O I I I O O I/O I/O I I I I I O I I I PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DESCRIPTION Segment Driver POL/AC Backplane 2 Backplane 1 V+ VReference Input Lo Hi Deintegrate Analog Common Int I Int V/ Triple Point Auto Zero Capacitor (CAZ) Integrate Capacitor (CINT) Beeper Output mA/A /V/A Hi DC/Lo AC I/O I O I O O O O O O O O O O O O O PIN NUMBER 20 21 22 23 24 25 26 27 28 29 32 33 34 35 39 40 Hold Oscillator Out Oscillator In Segment DRIVER k/m Segment Driver /A Segment Driver M /A Segment Driver Lo Bat/V Segment Driver B0 /C0 Segment Driver A0 /D0 Segment Driver G0 /E0 Segment Driver A1 /D1 Segment Driver G1 /E1 Segment Driver F1 /DP1 Segment Driver B2 /C1 Segment Driver B3 /C3 Segment Driver ADG3 /E3 DESCRIPTION
NOTE: For segment drivers, segments are listed as (segment for backplane 1)/(segment for backplane 2). Example: pin 27; segment B0 is on backplane 1, segment C0 is on backplane 2.
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ICL7139, ICL7149 Detailed Description
General The Functional Block Diagram shows the digital section which includes all control logic, counters, and display drivers. The digital section is powered by V+ and Digital Common, which is about 3V below V+. The oscillator is also in the digital section. Normally 120kHz for rejection of 60Hz AC interference and 100kHz for rejection of 50Hz AC should be used. The oscillator output is divided by two to generate the internal master clock. The analog section contains the integrator, comparator, reference section, analog buffers, and several analog switches which are controlled by the digital logic. The analog section is powered from V+ and V-.
DIGIT 3 LOW BATT 2 1 0
DC Voltage Measurement Autozero Only those portions of the analog section which are used during DC voltage measurements are shown in Figure 3. As shown in the timing diagram (Figure 1), each measurement starts with an autozero (AZ) phase. During this phase, the integrator and comparator are configured as unity gain buffers and their non-inverting inputs are connected to Common. The output of the integrator, which is equal to its offset, is stored on CAZ - the autozero capacitor. Similarly, the offset of the comparator is stored in ClNT . The autozero cycle equals 1000 clock cycles which is one 60Hz line cycle with a 120kHz oscillator, or one 50Hz line cycle with a 100kHz oscillator. Range 1 Integrate
a g d
f e
b k M c mAV A
AC DP3 DP2 DP1
The ICL7139 and ICL7149 perform a full autorange search for each reading, beginning with range 1. During the range 1 integrate period, internal switches connect the INT V/ terminal to the Triple Point (Pin 13). The input signal is integrated for 10 clock cycles, which are gated out over a period of 1000 clock cycles to ensure good normal mode rejection of AC line interference.
FIGURE 2. DISPLAY SEGMENT NOMENCLATURE
RDEINT TRIPLE POINT CAZ CAZ CINT CINT RDEINT
VIN
INT V/ RINTV T
T
AZ AZ
DEINTAZ
DEINTVREF
AZ + INTEGRATOR
-
VREF DEINT+ DEINT+
+ COMPARATOR TO LOGIC SECTION
-
V+ 6.7V ANALOG COMMON COMMON
+
-
T = (INT)(AR)(AZ) AR = AUTORANGE CHOPPER AZ = AUTOZERO INT = INTEGRATE
80A V-
FIGURE 3. DETAILED CIRCUIT DIAGRAM FOR DC VOLTAGE MEASUREMENT
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ICL7139, ICL7149
Range 1 Deintegrate At the beginning of the deintegrate cycle, the polarity of the voltage on the integrator capacitor (CINT) is checked, and either the DElNT+ or DElNT- is asserted. The integrator capacitor CINT is then discharged with a current equal to VREF/RDElNT . The comparator monitors the voltage on CINT . When the voltage on CINT is reduced to zero (actually to the VOS of the comparator), the comparator output switches, and the current count is latched. If the CINT voltage zero-crossing does not occur before 4000 counts have elapsed, the overload flag is set. "OL" (overload) is then displayed on the LCD. If the latched result is between 360 and 3999, the count is transferred to the output latches and is displayed. When the count is less than 360, an underrange has occurred, and the ICL7139 and ICL7149 then switch to range 2 - the 40V scale. Range 2 The range 2 measurement begins with an autozero cycle similar to the one that preceded range 1 integration. Range 2 cycle length however, is one AC line cycle, minus 360 clock cycles. When performing the range 2 cycle, the signal is integrated for 100 clock cycles, distributed throughout one line cycle. This is done to maintain good normal mode rejection. Range 2 sensitivity is ten times greater than range 1 (100 vs 10 clock cycle integration) and the full scale voltage of range 2 is 40V. The range 2 deintegrate cycle is identical to the range 1 deintegrate cycle, with the result being displayed only for readings greater than 360 counts. If the reading is below 360 counts, the ICL7139 and ICL7149 again asserts the internal underrange signal and proceeds to range 3. Range 3 The range 3V or 4V full scale measurement is identical to the range 2 measurement, except that the input signal is integrated during the full 1000 clock cycles (one line frequency cycle). The result is displayed if the reading is greater than 360 counts. Underrange is asserted, and a range 4 measurement is performed if the result is below 360 counts. Range 4 This measurement is similar to the range 1, 2 and 3 measurements, except that the integration period is 10,000 clock cycles (10 line cycles) long. The result of this measurement is transferred to the output latches and displayed even if the reading is less than 360. Autozero After finding the first range for which the reading is above 360 counts, the display is updated and an autozero cycle is entered. The length of the autozero cycle is variable which results in a fixed measurement period of 24,000 clock cycles (24 line cycles). DC Current Figure 4 shows a simplified block diagram of the analog section of the ICL7139 and ICL7149 during DC current measurement. The DC current measurements are very similar to DC voltage measurements except: 1) The input voltage is developed by passing the input current through a 0.1 (HI current ranges), or 9.9 (LOW current ranges)
RDEINT TRIPLE POINT CAZ CAZ CINT CINT RDEINT
INT I
LOW I
I
T
AZ AZ
DEINT-
DEINTVREF
RINTI T 9.9 VREF
HIGH I
AZ + INTEGRATOR
AZ
-
+ COMPARATOR TO LOGIC SECTION
-
DEINT+
DEINT+
V+ 0.1 ANALOG COMMON COMMON 6.7V
+
-
T = (INT)(AR)(AZ) AR = AUTORANGE CHOPPER AZ = AUTOZERO INT = INTEGRATE
80A V-
FIGURE 4. DETAILED CIRCUIT DIAGRAM FOR DC CURRENT MEASUREMENT
3-38
ICL7139, ICL7149
current sensing resistor; 2) Only those ranges with 1000 and 10,000 clock cycles of integration are used; 3) The RlNT l resistor is 1M, rather than the 10M value used for the RlNT V resistor. By using the lower value integration resistor, and only the 2 most sensitive ranges, the voltage drop across the current sensing resistor is 40mV maximum on the 4mA and 400mA ranges; 400mV maximum on the 40mA and 4A scales. With some increase in noise, these "burden" voltages can be reduced by lowering the value of both the current sense resistors and the RlNT l resistor proportionally. The DC current measurement timing diagram is similar to the DC voltage measurement timing diagram, except in the DC current timing diagram, the first and second integrate and deintegrate phases are skipped. AC Voltage Measurement for ICL7139 As shown in Figure 5, the AC input voltage is applied directly to the ICL7139 input resistor. No separate AC to DC conversion circuitry is needed. The AC measurement cycle is begun by disconnecting the integrator capacitor and using the integrator as an autozeroed comparator to detect the positive-going zero crossing. Once synchronized to the AC input, the autozero loop is closed and a normal integrate/deintegrate cycle begins. The ICL7139 resynchronizes itself to the AC input prior to every reading. Because diode D4 is in series with the integrator capacitor, only positive current from the integrator flows into the integrator capacitor, ClNT . Since the voltage on ClNT is proportional to the half-wave rectified average AC input voltage, a conversion factor must be applied to convert the reading to RMS. This conversion factor is /22 = 1.1107, and the system clock is manipulated to perform the RMS conversion. As a result the deintegrate and autozero cycle times are reduced by 10%. AC Voltage Measurement for ICL7149 The ICL7149 is designed to be used with an optional AC to DC voltage converter circuit. It will autorange through two voltage ranges (400V and 40V), and the AC annunciator is enabled. A typical averaging AC to DC converter is shown in Figure 6, while an RMS to DC converter is shown in Figure 7. AC current can also be measured with some simple modifications to either of the two circuits in Figures 6 and 7.
RDEINT CAZ TRIPLE POINT CINT CAZ CINT 5 ACINT D1 ACS D2 VREF D4 DEINTDEINT DEINT
~
INT V/ RINTV T
T
D3 ACINT AZ ACS AZ + INTEGRATOR
AZ
-
+ COMPARATOR
-
AC IN V+ 6.7V
~
COMMON
+
-
S = AZ * ACS * ACINT T = (INT + ACS) AZ AR ACS = AC SYNC AR = AUTORANGE CHOPPER AZ = AUTOZERO INT = INTEGRATE 80A
V-
FIGURE 5. DETAILED CIRCUIT DIAGRAM FOR AC VOLTAGE MEASUREMENT FOR ICL7139 ONLY
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ICL7139, ICL7149
1.0F
100k V+ V-
11 20M VIN 0VAC - 400VAC 0Hz - 1000Hz 100k 1 0.1F V+ VICL7149 7 10 2 8 1 0.1F COM 0.1F 10 COMMON 0.1F 4 50k
ICL7652 8
7 10 2
43.2k
5k 12 INT (V/) FULL SCALE ADJUST
5+
11 20M 4
ICL7652
5+
FIGURE 6. AC VOLTAGE MEASUREMENT USING OPTIONAL AVERAGING CIRCUIT
2.2F
+
V+ 2.2F 1
+
7 3 6 5 4 FULL SCALE ADJUST 5k 12 INT (V/)
VIN 0VAC - 400VAC 50Hz - 1000Hz
10M
2 AD736
8
+
10F
4.99k
V-
V+ ICL7149
30k
10 COM COMMON
FIGURE 7. AC VOLTAGE MEASUREMENT USING OPTIONAL RMS CONVERTER CIRCUIT
3-40
ICL7139, ICL7149
RDEINT TRIPLE POINT CAZ CAZ CINT CINT RDEINT
INT V/ RINTV T
T
AZ AZ AZ + INTEGRATOR
AZ
-
+ LO RX RKNOWN 1 HI RKNOWN 2 COMMON LOW LOW +
-
-
DEINT+
DEINT+
COMPARATOR
TO LOGIC SECTION
+
-
VREF T = INT + DEINT AZ = AUTOZERO INT = INTEGRATE
FIGURE 8. DETAILED CIRCUIT DIAGRAM FOR RATIOMETRIC MEASUREMENT
Ratiometric Measurement The ratiometric measurement is performed by first integrating the voltage across an unknown resistor, RX , then effectively deintegrating the voltage across a known resistor (RKNOWN1 or RKNOWN2 of Figure 8). The shunting effect of RINTV does not affect the reading because it cancels exactly between integration and deintegration. Like the current measurements, the measurements are split into two sets of ranges. LO measurements use a 10k reference resistor, and the full scale ranges are 4k and 40k. HI measurements use a 1M reference resistor, and the full scale ranges are 0.4M and 4M. The measurement phases and timing are the same as the measurement phases and timing for DC current except: 1) During the integrate phases the input voltage is the voltage across the unknown resistor RX , and; 2) During the deintegrate phases, the input voltage is the voltage across the reference resistor RKNOWN1 or RKNOWN2 . Continuity Indication When the ICL7139 and ICL7149 are in the LO measurement mode, the continuity circuit of Figure 9 will be active. When the voltage across RX is less than approximately 100mV, the beeper output will be on. When RKNOWN is 10k, the beeper output will be on when RX is less than 1k.
LO
Common Voltage The analog and digital common voltages of the ICL7139 and ICL7149 are generated by an on-chip resistor/zener/diode combination, shown in Figure 10. The resistor values are chosen so the coefficient of the diode voltage cancels the positive temperature coefficient of the zener voltage. This voltage is then buffered to provide the analog common and the digital common voltages. The nominal voltage between V+ and analog common is 3V. The analog common buffer can sink about 20mA, or source 0.01mA, with an output impedance of 10. A pullup resistor to V+ may be used if more sourcing capability is desired. Analog common may be used to generate the reference voltage, if desired.
V+ 80A 6.7V 125K + 3V + 3.1V
ANALOG COMMON P (PIN 10)
LOGIC SECTION
5K
+
+ 180K
-
DIGITAL COMMON P (INTERNAL)
LO BAT
-+ 0.3V + V-
RKNOWN
HI +
+
-
LO VREF
V+ BEEPER OUTPUT V+
FIGURE 10. ANALOG AND DIGITAL COMMON VOLTAGE GENERATOR CIRCUIT
-
Oscillator The ICL7139 and ICL7149 use a parallel resonant-type crystal in a Pierce oscillator configuration, as shown in Figure 11, and requires no other external components. The crystal eliminates the need to trim the oscillator frequency. An external signal may be capacitively coupled in OSC IN, with a signal level between 0.5V and 3VP-P . Because the
RUNKNOWN
RX COM
+
-
2kHz VX VX = 100mV
FIGURE 9. CONTINUITY BEEPER DRIVE CIRCUIT
3-41
ICL7139, ICL7149
OSC OUT pin is not designed to drive large external loads, loading on this pin should not exceed a single CMOS input. The oscillator frequency is internally divided by two to generate the ICL7139 and ICL7149 clock. The frequency should be 120kHz to reject 60Hz AC signals, and 100kHz to reject 50Hz signals.
OSC IN 5M 330K OSC OUT
Ternary Input The /Volts/Amps logic input is a ternary, or 3-level input. This input is internally tied to the common voltage through a high-value resistor, and will go to the middle, or "Volts" state, when not externally connected. When connected to V-, approximately 5A of current flows out of the input. In this case, the logic level is the "Amps", or low state. When connected to V+, about 5A of current flows into the input. Here, the logic level is the "", or high state. For other pins, see Table 2.
TABLE 2. TERNARY INPUTS CONNECTIONS
5pF
10pF
PIN NUMBER 17 18 19 20
V+ mA Hi/DC Hold
OPEN OR COM A V Lo/AC Auto
VTest Amps Test Test
FIGURE 11. INTERNAL OSCILLATOR CIRCUIT DIAGRAM
Display Drivers Figure 12 shows typical LCD Drive waveforms, RMS ON, and RMS OFF voltage calculations. Duplex multiplexing is used to minimize the number of connections between the ICL7139 and ICL7149 and the LCD. The LCD has two separate backplanes. Each drive line can drive two individual segments, one referenced to each backplane. The ICL7139 and ICL7149 drive 33/4 7-segment digits, 3 decimal points, and 11 annunciators. Annunciators are used to indicate polarity, low battery condition, and the range in use. Peak drive voltage across the display is approximately 3V. An LCD with approximately 1.4VRMS threshold voltage should be used. The third voltage level needed for duplex drive waveforms is generated through an on-chip resistor string. The DC component of the drive waveforms is guaranteed to be less than 50mV.
Component Selection For optimum performance while maintaining the low-cost advantages of the ICL7139 and ICL7149, care must be taken when selecting external components. This section reviews specifications and performance effects of various external components.
BACKPLANE
VPEAK V+ VPEAK / 2 O DCOM VPEAK O VPEAK
V RMS =
5 -- V PEAK ON 8 5 -- V PEAK OFF 8
SEGMENT ON
V RMS =
VPEAK = 3V 10% RMS ON 2.37V RMS OFF 1.06V
SEGMENT OFF
O 2VPEAK O (VOLTAGE ACROSS ON SEGMENT)
VSEGMENT ON
-2VPEAK VPEAK
(VOLTAGE ACROSS OFF SEGMENT)
VSEGMENT OFF
O -VPEAK
FIGURE 12. DUPLEXED LCD DRIVE WAVEFORMS
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ICL7139, ICL7149
Integrator Capacitor, ClNT As with all dual-slope integrating convertors, the integration capacitor must have low dielectric absorption to reduce linearity errors. Polypropylene capacitors add undetectable errors at a reasonable cost, while polystyrene and polycarbonate may be used in less critical applications. The ICL7139 and ICL7149 are designed to use a 3.3nF (0.0033F) ClNT with an oscillator frequency of 120kHz and an RlNTV of 10M. With a 100kHz oscillator frequency (for 50Hz line frequency rejection), ClNT and RINTV affects the voltage swing of the integrator. Voltage swing should be as high as possible without saturating the integrator. Saturation occurs when the integrator output is within 1V of either V+ or V-. Integrator voltage swing should be about 2V when using standard component values. For different RlNTV and oscillator frequencies the value of ClNT can be calculated from:
( Integrate Time ) x ( Integrate Current ) C INT = --------------------------------------------------------------------------------------------------( Desired Integrator Swing ) ( 10,000 x 2 x Oscillator Period ) x 0.4V/R INTV = ------------------------------------------------------------------------------------------------------------------------( 2V )
The ideal CAZ is a low leakage polypropylene or Teflon capacitor. Other film capacitors such as polyester, polystyrene, and polycarbonate introduce negligible errors. If a few seconds of settling time upon power-up is acceptable, the CAZ may be a ceramic capacitor, provided it does not have excessive leakage. Ohm Measurement Resistors Because the ICL7139 and ICL7149 use a ratiometric ohm measurement technique, the accuracy of ohm reading is primarily determined by the absolute accuracy of the RKNOWN1 and RKNOWN2 . These should normally be 10k and 1M, with an absolute accuracy of at least 0.5%. Current Sensing Resistors The 0.1 and 9.9 current sensing resistors convert the measured current to a voltage, which is then measured using RlNT l. The two resistors must be closely matched, and the ratio between RlNT l and these two resistors must be accurate - normally 0.5%. The 0.1 resistor must be capable of handling the full scale current of 4A, which requires it to dissipate 1.6W. Continuity Beeper The Continuity Beeper output is designed to drive a piezoelectric transducer at 2kHz (using a 120kHz crystal), with a voltage output swing of V+ to V-. The beeper output off state is at the V+ rail. When crystals with different frequencies are used, the frequency needed to drive the transducer can be calculated by dividing the crystal frequency by 60. Display The ICL7139 and ICL7149 use a custom, duplexed drive display with range, polarity, and low battery annunciators. With a 3V peak display voltage, the RMS ON voltage will be 2.37V minimum; RMS OFF voltage will be 1.06V maximum. Because the display voltage is not adjustable, the display should have a 10% ON threshold of about 1.4V. Most display manufacturers supply a graph that shows contrast versus RMS drive voltage. This graph can be used to determine what the contrast ratio will be when driven by the ICL7139 and ICL7149. Most display thresholds decrease with increasing temperature. The threshold at the maximum operating temperature should be checked to ensure that the "off" segments will not be turned "on" at high temperatures. Crystal The ICL7139 and ICL7149 are designed to use a parallel resonant 120kHz or 100kHz crystal with no additional external components. The RS parameter should be less than 25k to ensure oscillation. Initial frequency tolerance of the crystal can be a relatively loose 0.05%. Switches Because the logic input draws only about 5A, switches driving these inputs should be rated for low current, or "dry" operations. The switches on the external inputs must be able to reliably switch low currents, and be able to handle voltages in excess of 400VAC .
Integrator Resistors The normal values of the RlNT V and RlNT l resistors are 10M and 1M respectively. Though their absolute values are not critical, unless the value of the current sensing resistors are trimmed, their ratio should be 10:1, within 0.05%. Some carbon composition resistors have a large voltage coefficient which will cause linearity errors on the 400V scale. Also, some carbon composition resistors are very noisy. The class "A" output of the integrator begins to have nonlinearities if required to sink more than 70A (the sourcing limit is much higher). Because RlNT V drives a virtual ground point, the input impedance of the meter is equal to R lNT V . Deintegration Resistor, RDElNT Unlike most dual-slope A/D converters, the ICL7139 and ICL7149 use different resistors for integration and deintegration. RDElNT should normally be the same value as RlNT V , and have the same temperature coefficient. Slight errors in matching may be corrected by trimming the reference voltage. Autozero Capacitor, CAZ The CAZ is charged to the integrator's offset voltage during the autozero phases, and subtracts that voltage from the input signal during the integrate phases. The integrator thus appears to have zero offset voltage. Minimum CAZ value is determined by: 1) Circuit leakages; 2) CAZ self-discharge; 3) Charge injection from the internal autozero switches. To avoid errors, the CAZ voltage change should be less than 1/10 of a count during the 10,000 count clock cycle integration period for the 400mV range. These requirements set a lower limit of 0.047F for CAZ but 0.1F is the preferred value. The upper limit on the value of CAZ is set by the time constant of the autozero loop, and the 1 line cycle time period allotted to autozero. CAZ may be several 10s of F before approaching this limit.
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ICL7139, ICL7149
Reference Voltage Source A voltage divider connected to V+ and Common is the simplest source of reference voltage. While minimizing external component count, this approach will provide the same voltage tempco as the ICL7139 and ICL7149 Common - about 100PPM/oC. To improve the tempco, an ICL8069 bandgap reference may be used (see Figure 13). The reference voltage source output impedance must be RDElNT/4000.
V+ 10M
Applications, Examples, and Hints A complete autoranging 33/4 digit multimeter is shown in Figure 14. The following sections discuss the functions of specific components and various options. Meter Protection The ICL7139 and ICL7149 and their external circuitry should be protected against accidental application of 110/220V AC line voltages on the and current ranges. Without the necessary precautions, both the ICL7139 and ICL7149 and their external components could be damaged under such fault conditions. For the current ranges, fast-blow fuses should be used between S5A in Figure 14 and the 0.1 and 9.9 shunt resistors. For the ranges, no additional protection circuitry is required. However, the 10k resistor connected to pin 7 must be able to dissipate 1.2W or 4.8W for short periods of time during accidental application of 110V or 220VAC line voltages respectively.
10K 10M ICL8069 10K 1M
TRIPLE POINT DEINTEGRATE INTEGRATE VOLT/ INTEGRATE CURRENT
EXTERNAL REFERENCE
REFERENCE INPUT ANALOG COMMON
FIGURE 13. EXTERNAL VOLTAGE REFERENCE CONNECTION TO ICL7139 AND ICL7149
10M 0.1F 13
3.3nF
120kHz CRYSTAL 21 22
14
15
INPUTS V/ V S4A A S5A A A mA
TRIPLE CAZ CINT OSC OSC OUT IN POINT 9 DEINT DISPLAY 10M 12 DRIVE INT (V/) OUTPUTS 10k 7 LO 1M 8 HI BEEPER 1M 11 INT (I) V+ ICL7139 9.9 ICL7149
LO BAT 1-3 23-40 AC 16 4 + + 1F ON/OFF 9V BATTERY BEEPER
mAVA
kM
PIN 4
S1 4.7F + 10k TANT
10k
COMMON
30K50K V
0.1 2W 10 COMMON VVREF V//A HI-DC/LO-AC 17 mA/A
5 6 19 S3 V+ V+
ICL8069 PIN 10
V+ A V+ VmA
18 A S4B
20 HOLD
S3
S2 CLOSED: HI-DC S3 CLOSED: HOLD READING
NOTES: 1. Crystal is a Statek or SaRonix CX-IV type. 2. Multimeter protection components have not been shown. 3. Display is from LXD, part number 38D8R02H (or Equivalent). 4. Beeper is from muRata, part number PKM24-4A0 (or Equivalent). FIGURE 14. BASIC MULTIMETER APPLICATION CIRCUIT FOR ICL7139 AND ICL7149
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ICL7139, ICL7149
Printed Circuit Board Layout Considerations Particular attention must be paid to rollover performance, leakages, and guarding when designing the PCB for a ICL7139 and ICL7149 based multimeter. The rollover error causes the width of the +0 count to be larger than normal. The ICL7139 and ICL7149 will thus read zero until several hundred microvolts are applied in the positive direction. The ICL7139 and ICL7149 will read -1 when approximately -100V is applied. The rollover error can be minimized by guarding the Triple Point and CAZ nodes with a trace connected to the ClNT pin, (see Figure 15) which is driven by the output of the integrator. Guarding these nodes with the output of the integrator reduces the stray capacitance to ground, which minimizes the charge error on ClNT and CAZ . If possible, the guarding should be used on both sides of the PC board. Stray Pickup
FIGURE 15. PC BOARD LAYOUT
9
10
11
12
13
14 15
Rollover Performance, Leakages, and Guarding Because the ICL7139 and ICL7149 system measures very low currents, it is essential that the PCB have low leakage. Boards should be properly cleaned after soldering. Areas of particular importance are: 1) The INT V/ and INT l Pins; 2) The Triple Point; 3) The RDElNT and the CAZ pins. The conversion scheme used by the ICL7139 and ICL7149 changes the common mode voltage on the integrator and the capacitors CAZ and ClNT during a positive deintegrate cycle. Stray capacitance to ground is charged when this occurs, removing some of the charge on ClNT and causing rollover error. Rollover error increases about 1 count for each picofarad of capacitance between CAZ or the Triple Point and ground, and is seen as a zero offset for positive voltages. Rollover error is not seen as gain error.
While the ICL7139 and ICL7149 have excellent rejection of line frequency noise and pickup in the DC ranges, any stray coupling will affect the AC reading. Generally, the analog circuitry should be as close as possible to the ICL7139 and ICL7149. The analog circuitry should be removed or shielded from any 120V AC power inputs, and any AC sources such as LCD drive waveforms. Keeping the analog circuit section close to the ICL7139 and ICL7149 will also help keep the area free of any loops, thus reducing magnetically coupled interference coming from power transformers, or other sources.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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